Text Books

Book 1
Digital Integrated Circuits Edition 1 - Prentice Hall 1995

Digital Integrated Circuits
Edition 1, 1995
Prentice Hall

Digital Integrated Circuits
Edition 2, 2003
Prentice Hall

Monographs and Booklets

Of Brains and Computers
December 2022
NOW, Foundations and Trends in Integrated Circuits and Systems

CHIPS: Hoe digitale technologie de wereld verandert
April 15, 2024
Academia Press

Edited Books

• B. Otis and J. Rabaey, "Ultra-low Power Wireless Technologies for Sensor Networks", Springer-Verlag, 2007.

• W. Weber, J.M. Rabaey and E. Aerts, Eds, "Ambient Intelligence," Springer-Verlag, 2005.

• S. Roundy, P. Wright and J.M. Rabaey, "Energy Scavenging for Wireless Sensor Networks," Kluwer Academic Publishers, 2003.

•  M. Pedram and J. Rabaey, Eds, "Power-Aware Design Methodologies," Kluwer Academic Publishers, 2002.

• V. George and J. Rabaey, "Low-Energy FPGAs," Kluwer Academic Publishers, 2001.

• J. Rabaey and M. Pedram, Eds, "Low Power Design Methodologies", Kluwer Academic Publishers, 1996.

• J. Encarnacao and J, Rabaey, Eds, "Mobile Communications: Technology, tools, applications, authentication and security," Kluwer Academic Publishers, 1996.

BOOK CHAPTERS

    ■      J. Rabaey, Brain-like Cognitive Engineering Systems, in “From Artificial Intelligence to Brain Intelligence, ,” Rivers Publishers, pp. 101-134, September 2022.

■      R. Muller, S. Gambini and J. Rabaey, in “Handbook of Bioelectronics,” Ed. Sandro Carrara and Kris Iniewski, January 2015.

     ■      BP Otis, N Pletcher, J Rabaey, A MEMS-Enabled Two-Receiver Chipset for Asynchronous Networks, in MEMS-based Circuits and Systems for Wireless Communication, pp. 235-257, Springer 2013.

     ■      J. Rabaey, Y. Chee, D. Chen, L. de Nardis, S. Gambini, D. Guermandi, M. Mark and N. Pletcher, “Short-Distance Wireless and its Opportunities,” in Wireless Technologies, Ed. Kris Iniewski, pp 159-184, CRC Press, 2008.

     ■      Brian Otis, Nathan Pletcher, Shailesh Rai, and Jan Rabaey, "Low Power Techniques for Wireless Sensing",  in Advances in Analog Circuit Design, Springer Press,  Nov 2006.

     ■      B.P. Otis, Y.H. Chee, R. Lu, N.M. Pletcher, S. Gambini†, J.M. Rabaey, "Highly Integrated Ultra-Low Power RF Transceivers for Wireless Sensor Networks", in Low-Power Electronics Design, Editor C.Piguet, CRC Press, 2005.

     ■      J. Rabaey, "System-on-a-Chip Challenges in the Deep-Submicron Era - A case for the network-on-a-Chip", in Interconnect-Centric Design for Advanced SOC and NOC, Kluwer Academic Publishers, Editor Jari Nurmi, 2004, pp. 3-24.

     ■      A. Chandrakasan, M. Potkonjak, J. Rabaey and R. Brodersen, "Hyper-LP: A System for Power Minimization Using Architectural Transformations," in The Best of ICCAD, 20 Years of Excellence in Computer-Aided Design, A. Kuehlman Ed., Kluwer Academic Publishers, 2003, pp. 117-127.

     ■      G. Goossens, J. Rabaey, J. Vandewalle and H. De Man, "An efficient microcode-compiler for custom DSP-processors",  in The Best of ICCAD, 20 Years of Excellence in Computer-Aided Design, A. Kuehlman Ed., Kluwer Academic Publishers, 2003, pp. 107-116.

     ■      H. De Man and J. Rabaey, "System Design and Analysis Overview," in The Best of ICCAD, 20 Years of Excellence in Computer-Aided Design, A. Kuehlman Ed., Kluwer Academic Publishers, 2003, pp. 93-106

     ■      A. Abnous, H. Zhang, M. Wan, G. Varghese, V,. Prabhu, and J. Rabaey, "The Pleiades Architecture," in The Application of Programmable DSPs in Mobile Communications, A. Gatherer and A. Auslander, Ed., Wiley, 2002, pp. 327-360.

     ■      J. Rabaey et al, "Hybrid Reconfigurable Processors —The Road to Low-Power Programmable Computing", Book Chapter, T. Sakurai Editor,  Realize, Inc, Japan.

     ■      A. Chandrakasan, M. Potkonjak, J. Rabaey and R. Brodersen, "Hyper-LP: A System for Power Minimization Using Architectural Transformations," in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp.578-581, IEEE Press, 1998.

     ■      R. Mehra, L. Guerra, J. Rabaey, "Exploiting Locality for Low-Power Design,"  in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp.574-577, IEEE Press, 1998.

     ■      P. Landman and J Rabaey, "Activity Sensitive Architectural Power Analysis", in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp.516-532, IEEE Press, 1998.

     ■      D. Lidsky, J. Rabaey, "Low-Power Design of Memory Intensive Functions Case Study: Vector Quantization," in Low Power CMOS Design, A. Chandrakasan and R. Brodersen, Ed., pp. 433-436, IEEE Press, 1998.

     ■      J. Rabaey, M. Pedram and P. Landman, "Low Power Design Methodologies - Introduction",   Low Power Design Methodologies, J. Rabaey and M. Pedram, Ed., Kluwer Academic Publishers, Boston, 1996.

     ■      R. Mehra, D. Lidsky, A. Abnous, P.E. Landman, J. Rabaey, "Algorithm and Architecture Level Methodologies," Low Power Design Methodologies, J. Rabaey and M. Pedram, Ed., Kluwer Academic Publishers, Boston, 1996.

     ■      J. Rabaey, "Low Power Digital Design," Circuits and Systems Tutorials, Ed. Chris Toumazou, pp 373-386. LTP Electronics, Oxford, UK, June 1994.

     ■      M. Potkonjak and J. Rabaey, "Exploring the Algorithmic DEsign Space using High Level Synthesis", in "High Level Synthesis", by M. Bayoumi, Kluwer Academic, December 1993.

     ■      J. Rabaey, C. Chu, P. Hoang and M. Potkonjak, "Synthesis of Datapath Architectures", in Anatomy of a Silicon Compiler, Kluwer Academic Publishers, pp. 221-250, Fall 1992.

     ■      P. Hilfinger and J. Rabaey, "DSP Specification Using the Silage Language", in Anatomy of a Silicon Compiler, Kluwer Academic Publishers, pp. 199-220, Fall 1992.

     ■      S. Lee and J. Rabaey, "Interactive Floorplanning", in Anatomy of a Silicon Compiler, Kluwer Academic Publishers, pp 103-126, Fall 1992.

     ■      J. Rabaey, T. Stoelzle, D. Chen, S. Narayansswamy, R. Brodersen, H. Murveit and A. Santos,"A Large Vocabulary Real Time Connected Speech Recognition System", in VLSI Signal Processing III, IEEE Press, pp 61-74, November 1988.

     ■      W. Koh, A. Yeung, P. Hoang and J. Rabaey, "A Multi-Processor System for DSP Behavioral Simulation", in VLSI Signal Processing III, IEEE Press, pp. 295-306, November 1988.

     ■      J. Rabaey, H. De Man, J. Vanhoof, G. Goossens and F. Catthoor,"CATHEDRAL-II : A Synthesis System for Multiprocessor DSP Systems", in "Silicon Compilation", Addison-Wesley, December 1987.

     ■      S. Pope, J. Rabaey and R. Brodersen, "Automatic Generation of Digital Signal Processing Circuits" NATO Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, 1986,in Design Synthesis for VLSI Circuits, Martinus Nijhoff Publishers, Dordrecht.

     ■      H. De Man, J. Rabaey, P. Six, "CATHEDRAL II : A Synthesis and Module Generation System for Multiprocessor Systems on a Chip", NATO Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, 1986, in Design Synthesis for VLSI Circuits, Martinus Nijhoff Publishers, Dordrecht.

     ■      S. Pope, J. Rabaey and R. Brodersen, "Automated design of signal processors using macrocells", in "VLSI Signal Processing", New York, IEEE Press 1984, pp. 239-251.

     ■      J. Rabaey, "A Unified Computer Aided Design technique for Switched capacitor Systems in the Time and the Frequency Domain", PhD. Dissertation, Katholieke Universiteit Leuven, April 1983.

     ■      H. De Man, J. Vandewalle and J. Rabaey, "Simulation of sampled data MOSLSI circuits", NATO ASI Conference on computer aids for VLSI-circuits, Urbino, Italy, July 1980, published by Sijthoff & Noordhoff, E 48, pp. 241-284.

     ■      H. De Man, J. Rabaey, G. Arnout and J. Vandewalle, "Practical implementation of a general computer aided design technique for switched capacitor circuits", Published in "Analog MOS Integrated Circuits", New York, IEEE Press, 1980.